#!/bin/csh -f
set name=$0
set name=${name:t} #当使用绝对路径比如：/xxx/bb/sim_ahb_vcs 运行时 截取最后一部分sim_ahb_vcs
if ( “$1″ =~ \-b* ) then
set build_only = 1
shift
else
set build_only = 0
endif
# 第一个参数 用 -b 或者 -bxxxx 就把 build_only设为1
if ( ! ${#argv} ) then
echo “ usage: ${name} <simulator> <control_lang> [-w]”
echo “ where <simulator> is one of: sciro vcsntb mtivlog vcsmxvhdlntb vcssv mtivhdl ncvlog vcsmxvlog vxl vcs vcsmxvlogntb vcsmxvhdl ncvhdl”
echo “ <control_lang> is one of: vera ntb C (default is native simulator language)”
echo “ -w enables simulator waves interactively”
exit( 1 )
endif
#如果没有参数 就打提醒信息
set simulator = $1
set waves = 0
if ( ${#argv} == 1 ) then
set control = “none”
endif
#如果是一个参数 设置control 为 “none”
if ( ${#argv} == 2 ) then
if ( “$2″ == \-w ) then
set control = “none”
set waves = 1
else
set control = $2
endif
endif
#如果是2个参数并且第二个参数是 -w 那么control=”none” waves=1，如果2个参数并且第二个参数不是-w那么control = 第二个参数
if ( ${#argv} == 3 ) then
set control = $2
if ( “$3″ == \-w ) then
set waves = 1
endif
endif
#如果是3个参数 control = 第2个参数，然后如果 第三个参数是-w那么wave=1
if ( ! $?DESIGNWARE_HOME) then
echo “Please set your DESIGNWARE_HOME environment variable”
exit( 1 )
endif
#如果DESIGNWARE_HOME环境没有设，打印错误信息
if ( ! $?VERA_HOME) then
if ( ${simulator} !~ *ntb && ${simulator} !~ *sv ) then
echo “Please set your VERA_HOME environment variable”
exit( 1 )
else
setenv VERA_HOME “”
endif
endif
#如果VERA_HOME环境没有设，并且simulator(第一个参数)既不是*ntb又不是*sv，提示需要设置。
#如果VERA_HOME环境没有设，并且simulator(第一个参数)是*ntb或是*sv，设置这个环境变量为空。
set design_dir = “/a/IDSP2/wub/amba/workspace/amba_vip_tutorial”
set include_dir = “${design_dir}/include”
set scenario_dir = “${design_dir}/examples/ahb_sys”
# SunOS:
set platform = “sparcOS5″
set ld = “ld”
set csupported = 1
set sysc_platform = “gccsparcOS5″
set sysc_ccflags = “”
set elf = “-lelf”
set ccflags = “”
set cdslibdirs = “-L/usr/dt/lib -L/usr/openwin/lib”
set cdslibs = “-ldwapi -ldcapi”
if ( ${VERA_HOME} =~ *solaris_64 ) then #如果VERA_HOME指向solaris64那么用64系列的变量
set vcsflags = “-full64″
set ccflags_dyn = “-Kpic -xarch=v9″
set ldflags_dyn = “-G -64″
set mti_tool_path = “sunos5v9″
else
set vcsflags = “”
set ccflags_dyn = “-Kpic”
set ldflags_dyn = “-G”
set mti_tool_path = “bin”
endif
set vcslibs = “”
set cdslibs2 = “-lvoids -ldl -lsocket -lnsl -lm -ldl -lw -lgen -lintl”
set mtilibs = “”
set sysscilib = “${VERA_HOME}/lib/libSysSciTaskpic.a”
set vuser_entry = “”
set cpplibs = “-lsocket”
set dyn_ext = “so”
set dyn_path_var = “LD_LIBRARY_PATH”
#
set path = ( ${VERA_HOME}/bin $path )
rm -f vera.ini
#simulator 第一个参数
switch ( ${simulator} )
case “vcs”:
set path = ( ${VCS_HOME}/bin $path )
#<control_lang> is one of: vera ntb C (default is native simulator language)
if ( ${control} == “none” ) then
if ( ${simulator} =~ *ntb || ${simulator} =~ *sv ) then
echo “NTB compliant simulators cannot be specified with native HDL control”
exit(1)
endif
cat << ! > hdl_files
${scenario_dir}/verilog/ahb_sys_tst.v
${include_dir}/verilog/ahb_monitor_vmt.v
${include_dir}/verilog/ahb_master_vmt.v
${include_dir}/verilog/ahb_slave_vmt.v
${include_dir}/verilog/ahb_bus_vmt.v
!
if (${waves}) then
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then #变量status 乃是用以显示最近的指令执行状态。执行成功状态为0；失败状态为1
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera +define+WAVES=yes ${vcslibs} -o simvcs -f hdl_files +plusarg_save +vcs+lic+wait +vpdports -I -notice”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera +define+WAVES=yes ${vcslibs} -o simvcs -f hdl_files +plusarg_save +vcs+lic+wait +vpdports -I -notice
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run +vera_full_conflict_info +vpdfile+vcdplus.vcd; vcs -RPP +vpdfile+vcdplus.vcd”
simvcs run +vera_full_conflict_info +vpdfile+vcdplus.vcd; vcs -RPP +vpdfile+vcdplus.vcd
if ( ${status} ) then
exit( 10 )
endif
endif
else
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run”
simvcs run
if ( ${status} ) then
exit( 10 )
endif
endif
endif
else if ( ${control} == “vera” ) then
if ( ${simulator} =~ *ntb || ${simulator} =~ *sv ) then
echo “NTB compliant simulators cannot be specified with Vera control”
exit(1)
endif
echo “# vera -cmp -I${include_dir}/vera -shell AhbSystemTest -vlog ${scenario_dir}/vera/ahb_sys_tst.vr”
vera -cmp -I${include_dir}/vera -shell AhbSystemTest -vlog ${scenario_dir}/vera/ahb_sys_tst.vr
if ( ${status} ) then
exit( 2 )
endif
cat << ! > hdl_files
${scenario_dir}/vera/ahb_sys_tst_vr.v
ahb_sys_tst_shell.v
!
if (${waves}) then
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera +define+WAVES=yes ${vcslibs} -o simvcs -f hdl_files +plusarg_save +vcs+lic+wait +vpdports -I -notice”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera +define+WAVES=yes ${vcslibs} -o simvcs -f hdl_files +plusarg_save +vcs+lic+wait +vpdports -I -notice
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run +vera_full_conflict_info +vpdfile+vcdplus.vcd +vera_load=ahb_sys_tst.vro; vcs -RPP +vpdfile+vcdplus.vcd +vera_load=ahb_sys_tst.vro”
simvcs run +vera_full_conflict_info +vpdfile+vcdplus.vcd +vera_load=ahb_sys_tst.vro; vcs -RPP +vpdfile+vcdplus.vcd +vera_load=ahb_sys_tst.vro
if ( ${status} ) then
exit( 10 )
endif
endif
else
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run +vera_load=ahb_sys_tst.vro”
simvcs run +vera_load=ahb_sys_tst.vro
if ( ${status} ) then
exit( 10 )
endif
endif
endif
else if ( ${control} == “ntb” ) then
if ( ${simulator} !~ *ntb && ${simulator} !~ *sv ) then
echo “Only NTB compliant simulators can be specified with NTB control”
exit(1)
endif
cat << ! > hdl_files
${include_dir}/vera/AhbMonitorSource.vrp
${include_dir}/vera/AhbMasterSource.vrp
${include_dir}/vera/AhbSlaveSource.vrp
${include_dir}/vera/AhbBusSource.vrp
${scenario_dir}/ntb/ahb_sys_tst.vr
${scenario_dir}/ntb/ahb_sys_tst_ntb.v
!
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files -ntb_incdir ${include_dir}/vera -ntb_incdir ${DESIGNWARE_HOME}/vip/vmt/2.70a/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_monitor_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_master_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_slave_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_bus_vmt/vera/src”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files -ntb_incdir ${include_dir}/vera -ntb_incdir ${DESIGNWARE_HOME}/vip/vmt/2.70a/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_monitor_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_master_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_slave_vmt/vera/src -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_bus_vmt/vera/src
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run”
simvcs run
if ( ${status} ) then
exit( 10 )
endif
endif
else if ( ${control} == “C” || ${control} == “c” ) then
if ( ${simulator} =~ *ntb || ${simulator} =~ *sv ) then
echo “NTB simulators cannot be specified with C control”
exit(1)
endif
if ( ! ${csupported} ) then
echo “C control is not supported on ${sysc_platform}”
exit( 1 )
endif
if ( ! $?CC ) then
echo “CC is not defined. To use C control, please set CC to a supported compiler and rerun.”
exit( 1 )
endif
setenv SYSTEMC_HOME ${DESIGNWARE_HOME}/vip/unsupported/systemc/latest
${CC} ${sysc_ccflags} -D${platform} -I${include_dir}/C -I${SYSTEMC_HOME}/include -I${VERA_HOME}/lib -c ${scenario_dir}/C/ahb_sys_tst.cpp
${CC} -o C.exe ahb_sys_tst.o ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_monitor_vmt/C/lib/${platform}/AhbMonitor.o ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_master_vmt/C/lib/${platform}/AhbMaster.o ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_slave_vmt/C/lib/${platform}/AhbSlave.o ${DESIGNWARE_HOME}/vip/amba/2.50a/ahb_bus_vmt/C/lib/${platform}/AhbBus.o ${DESIGNWARE_HOME}/vip/vmt/2.70a/C/lib/${platform}/VmtTBenchManager.o -L${SYSTEMC_HOME}/lib-${sysc_platform} -lsystemc ${cpplibs}
if ( ${status} ) then
exit( 2 )
endif
cat << ! > hdl_files
${scenario_dir}/C/ahb_sys_tst_c.v
${include_dir}/verilog/ahb_monitor_vmt.v
${include_dir}/verilog/ahb_master_vmt.v
${include_dir}/verilog/ahb_slave_vmt.v
${include_dir}/verilog/ahb_bus_vmt.v
!
echo “# rm -f simvcs”
rm -f simvcs
if ( ${status} ) then
exit( 9 )
endif
echo “# vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files”
vcs ${vcsflags} +incdir+${include_dir}/verilog -vera ${vcslibs} -o simvcs -f hdl_files
if ( ${status} ) then
exit( 9 )
endif
if ( ! ${build_only} ) then
echo “# simvcs run”
simvcs run
if ( ${status} ) then
exit( 10 )
endif
endif
else
echo “${name}: Unrecognized control language, ${control}.”
exit( 1 )
endif
breaksw
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